1. Field of the Invention
The present invention relates to data transfer, and more specifically to efficiently controlling data transfer between non-volatile memories and an IEEE 802.3 compliant physical layer device.
2. Description of the Related Art
FIG. 1 shows a part of the 10 Gigabit Ethernet architecture according to the IEEE 802.3ae, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specification, 2002 (“the IEEE 802.3ae Standard”). A MAC (Media Attachment Control) sublayer 101 connects a chip 100 consisting of a PMA (Physical Media Attachment) sublayer 103 and a PMD (Physical Media Dependent) sublayer 104 through a PCS (Physical Code Sublayer) 102. Although the PMA 103 and the PMD 104 are two logical blocks, they are conventionally grouped into one chip called PMA PMD, because both of them are analog related.
More and more manufacturers configure the PMD 104 according to Xenpak 10 Gigabit Ethernet MSA, a Cooperation Agreement for 10 Gigabit Ethernet Transceiver Package, versions 1.0, 2.0, 2.1 and 3.0 (“the Xenpak Specification”). The Xenpak Specification provides guidelines for pluggable fiber optic transceiver modules supporting implementations of the IEEE 802.3ae Standard. The Xenpak Specification requires that certain information, including the indication of transceiver capabilities, should be maintained in a set of external non-volatile memories, such as EEPROM (Electrically Erasable and Programmable Read Only Memory). Meanwhile, a physical layer device includes registers for storing instructions and data. The instructions and data can be downloaded to the registers from the non-volatile memories and uploaded from the registers to the non-volatile memories. The instructions and data are retained in the non-volatile memories when the power is lost and reloaded to the registers in the physical layer device with return of the power. A system controller controls the physical layer device to upload information from the registers in the physical layer device, thus updating the content of the non-volatile memories.
According to the Xenpak Specification, a top register 0x8000 is used for EEPROM control and status. This register defines commands and command statuses, but does not provide EEPROM address. To change one byte of information, the conventional method downloads the entire content of the EEPROM or uploads the entire content of the registers in the physical layer device. Consequently, the data transfer takes a long time and it is difficult to control other devices that can share the bus with an EEPROM.
Conventionally, pins are used to configure physical layer devices. After a chip is made, it is very difficult to change the pins and the configuration of the physical layer devices.
Therefore, it would be advantageous to provide an IEEE 802.3 compliant physical layer device which can transfer physical layer device configuration information with EEPROMs more efficiently and which can be configured more flexibly. It would also be advantageous to provide an IEEE 802.3 compliant physical layer device which facilitates control of devices sharing the bus with an EEPROM.